//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012-2013 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 149905
// File Date           :  2013-05-08 18:27:40 +0100 (Wed, 08 May 2013)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//------------------------------------------------------------------------------
// Purpose : HDL design file for AMBA master interface block
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//                               nic400_amib_sram_slv_axi4_ysyx_rv32.v
//                               =============
//
//------------------------------------------------------------------------------
//
//  Overview
// ==========
//
//   The Axi Master Interface Block provides an interface between an interconnect
// and an external slave port on NIC400.
//
//   The AMIB can be configured to provide four modes of operation for each of
// the channels:
//    1. fully registered (total timing isolation between
//                         master and slave ports)
//    2. forward path registered only (timing isolation on data/ctrl/valid
//                                     paths only)
//    3. reverse path registered only (timing isolation on ready paths only)
//
//------------------------------------------------------------------------------


`include "nic400_amib_sram_slv_axi4_defs_ysyx_rv32.v"

module nic400_amib_sram_slv_axi4_ysyx_rv32
  (
  
    //sram_slv_axi4_m AXI bus

    //AW Channel
    awid_sram_slv_axi4_m,
    awaddr_sram_slv_axi4_m,
    awlen_sram_slv_axi4_m,
    awsize_sram_slv_axi4_m,
    awburst_sram_slv_axi4_m,
    awlock_sram_slv_axi4_m,
    awcache_sram_slv_axi4_m,
    awprot_sram_slv_axi4_m,
    awvalid_sram_slv_axi4_m,
    awready_sram_slv_axi4_m,

    //W Channel
    wdata_sram_slv_axi4_m,
    wstrb_sram_slv_axi4_m,
    wlast_sram_slv_axi4_m,
    wvalid_sram_slv_axi4_m,
    wready_sram_slv_axi4_m,

    //B Channel
    bid_sram_slv_axi4_m,
    bresp_sram_slv_axi4_m,
    bvalid_sram_slv_axi4_m,
    bready_sram_slv_axi4_m,

    //AR Channel
    arid_sram_slv_axi4_m,
    araddr_sram_slv_axi4_m,
    arlen_sram_slv_axi4_m,
    arsize_sram_slv_axi4_m,
    arburst_sram_slv_axi4_m,
    arlock_sram_slv_axi4_m,
    arcache_sram_slv_axi4_m,
    arprot_sram_slv_axi4_m,
    arvalid_sram_slv_axi4_m,
    arready_sram_slv_axi4_m,

    //R Channel
    rid_sram_slv_axi4_m,
    rdata_sram_slv_axi4_m,
    rresp_sram_slv_axi4_m,
    rlast_sram_slv_axi4_m,
    rvalid_sram_slv_axi4_m,
    rready_sram_slv_axi4_m,

    //sram_slv_axi4_s AXI bus

    //AW Channel
    awid_sram_slv_axi4_s,
    awaddr_sram_slv_axi4_s,
    awlen_sram_slv_axi4_s,
    awsize_sram_slv_axi4_s,
    awburst_sram_slv_axi4_s,
    awlock_sram_slv_axi4_s,
    awcache_sram_slv_axi4_s,
    awprot_sram_slv_axi4_s,
    awvalid_sram_slv_axi4_s,
    awready_sram_slv_axi4_s,

    //W Channel
    wdata_sram_slv_axi4_s,
    wstrb_sram_slv_axi4_s,
    wlast_sram_slv_axi4_s,
    wvalid_sram_slv_axi4_s,
    wready_sram_slv_axi4_s,

    //B Channel
    bid_sram_slv_axi4_s,
    bresp_sram_slv_axi4_s,
    bvalid_sram_slv_axi4_s,
    bready_sram_slv_axi4_s,

    //AR Channel
    arid_sram_slv_axi4_s,
    araddr_sram_slv_axi4_s,
    arlen_sram_slv_axi4_s,
    arsize_sram_slv_axi4_s,
    arburst_sram_slv_axi4_s,
    arlock_sram_slv_axi4_s,
    arcache_sram_slv_axi4_s,
    arprot_sram_slv_axi4_s,
    arvalid_sram_slv_axi4_s,
    arready_sram_slv_axi4_s,

    //R Channel
    rid_sram_slv_axi4_s,
    rdata_sram_slv_axi4_s,
    rresp_sram_slv_axi4_s,
    rlast_sram_slv_axi4_s,
    rvalid_sram_slv_axi4_s,
    rready_sram_slv_axi4_s,

    //Clock and reset signals
    aclk,
    aresetn

  );




  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  //sram_slv_axi4_m AXI bus


  //AW Channel
  output  [3:0]       awid_sram_slv_axi4_m;         //write id of sram_slv_axi4_m AXI bus AW channel
  output  [31:0]      awaddr_sram_slv_axi4_m;       //write address of sram_slv_axi4_m AXI bus AW channel
  output  [7:0]       awlen_sram_slv_axi4_m;        //write length field of sram_slv_axi4_m AXI bus AW channel
  output  [2:0]       awsize_sram_slv_axi4_m;       //write size of sram_slv_axi4_m AXI bus AW channel
  output  [1:0]       awburst_sram_slv_axi4_m;      //write burst length of sram_slv_axi4_m AXI bus AW channel
  output              awlock_sram_slv_axi4_m;       //write lock of sram_slv_axi4_m AXI bus AW channel
  output  [3:0]       awcache_sram_slv_axi4_m;      //write cache field of sram_slv_axi4_m AXI bus AW channel
  output  [2:0]       awprot_sram_slv_axi4_m;       //write prot field of sram_slv_axi4_m AXI bus AW channel
  output              awvalid_sram_slv_axi4_m;      //write valid of sram_slv_axi4_m AXI bus AW channel
  input               awready_sram_slv_axi4_m;      //write ready of sram_slv_axi4_m AXI bus AW channel

  //W Channel
  output  [63:0]      wdata_sram_slv_axi4_m;        //write data of sram_slv_axi4_m AXI bus W Channel
  output  [7:0]       wstrb_sram_slv_axi4_m;        //write strobes of sram_slv_axi4_m AXI bus W Channel
  output              wlast_sram_slv_axi4_m;        //write last of sram_slv_axi4_m AXI bus W Channel
  output              wvalid_sram_slv_axi4_m;       //write valid of sram_slv_axi4_m AXI bus W Channel
  input               wready_sram_slv_axi4_m;       //write ready of sram_slv_axi4_m AXI bus W Channel

  //B Channel
  input   [3:0]       bid_sram_slv_axi4_m;          //b response id of sram_slv_axi4_m AXI bus B Channel
  input   [1:0]       bresp_sram_slv_axi4_m;        //b response status of sram_slv_axi4_m AXI bus B Channel
  input               bvalid_sram_slv_axi4_m;       //b response valid of sram_slv_axi4_m AXI bus B Channel
  output              bready_sram_slv_axi4_m;       //b response ready of sram_slv_axi4_m AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_sram_slv_axi4_m;         //read id of sram_slv_axi4_m AXI bus AR Channel
  output  [31:0]      araddr_sram_slv_axi4_m;       //read address of sram_slv_axi4_m AXI bus AR Channel
  output  [7:0]       arlen_sram_slv_axi4_m;        //read length of sram_slv_axi4_m AXI bus AR Channel
  output  [2:0]       arsize_sram_slv_axi4_m;       //read size of sram_slv_axi4_m AXI bus AR Channel
  output  [1:0]       arburst_sram_slv_axi4_m;      //read burst length of sram_slv_axi4_m AXI bus AR Channel
  output              arlock_sram_slv_axi4_m;       //read lock of sram_slv_axi4_m AXI bus AR Channel
  output  [3:0]       arcache_sram_slv_axi4_m;      //read cache field of sram_slv_axi4_m AXI bus AR Channel
  output  [2:0]       arprot_sram_slv_axi4_m;       //read prot field of sram_slv_axi4_m AXI bus AR Channel
  output              arvalid_sram_slv_axi4_m;      //read valid of sram_slv_axi4_m AXI bus AR Channel
  input               arready_sram_slv_axi4_m;      //read ready of sram_slv_axi4_m AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_sram_slv_axi4_m;          //read id of sram_slv_axi4_m AXI bus R Channel
  input   [63:0]      rdata_sram_slv_axi4_m;        //read data of sram_slv_axi4_m AXI bus R Channel
  input   [1:0]       rresp_sram_slv_axi4_m;        //read response status of sram_slv_axi4_m AXI bus R Channel
  input               rlast_sram_slv_axi4_m;        //read last of sram_slv_axi4_m AXI bus R Channel
  input               rvalid_sram_slv_axi4_m;       //read valid of sram_slv_axi4_m AXI bus R Channel
  output              rready_sram_slv_axi4_m;       //read ready of sram_slv_axi4_m AXI bus R Channel

  //sram_slv_axi4_s AXI bus


  //AW Channel
  input   [3:0]       awid_sram_slv_axi4_s;         //write id of sram_slv_axi4_s AXI bus AW channel
  input   [31:0]      awaddr_sram_slv_axi4_s;       //write address of sram_slv_axi4_s AXI bus AW channel
  input   [7:0]       awlen_sram_slv_axi4_s;        //write length field of sram_slv_axi4_s AXI bus AW channel
  input   [2:0]       awsize_sram_slv_axi4_s;       //write size of sram_slv_axi4_s AXI bus AW channel
  input   [1:0]       awburst_sram_slv_axi4_s;      //write burst length of sram_slv_axi4_s AXI bus AW channel
  input               awlock_sram_slv_axi4_s;       //write lock of sram_slv_axi4_s AXI bus AW channel
  input   [3:0]       awcache_sram_slv_axi4_s;      //write cache field of sram_slv_axi4_s AXI bus AW channel
  input   [2:0]       awprot_sram_slv_axi4_s;       //write prot field of sram_slv_axi4_s AXI bus AW channel
  input               awvalid_sram_slv_axi4_s;      //write valid of sram_slv_axi4_s AXI bus AW channel
  output              awready_sram_slv_axi4_s;      //write ready of sram_slv_axi4_s AXI bus AW channel

  //W Channel
  input   [63:0]      wdata_sram_slv_axi4_s;        //write data of sram_slv_axi4_s AXI bus W Channel
  input   [7:0]       wstrb_sram_slv_axi4_s;        //write strobes of sram_slv_axi4_s AXI bus W Channel
  input               wlast_sram_slv_axi4_s;        //write last of sram_slv_axi4_s AXI bus W Channel
  input               wvalid_sram_slv_axi4_s;       //write valid of sram_slv_axi4_s AXI bus W Channel
  output              wready_sram_slv_axi4_s;       //write ready of sram_slv_axi4_s AXI bus W Channel

  //B Channel
  output  [3:0]       bid_sram_slv_axi4_s;          //b response id of sram_slv_axi4_s AXI bus B Channel
  output  [1:0]       bresp_sram_slv_axi4_s;        //b response status of sram_slv_axi4_s AXI bus B Channel
  output              bvalid_sram_slv_axi4_s;       //b response valid of sram_slv_axi4_s AXI bus B Channel
  input               bready_sram_slv_axi4_s;       //b response ready of sram_slv_axi4_s AXI bus B Channel

  //AR Channel
  input   [3:0]       arid_sram_slv_axi4_s;         //read id of sram_slv_axi4_s AXI bus AR Channel
  input   [31:0]      araddr_sram_slv_axi4_s;       //read address of sram_slv_axi4_s AXI bus AR Channel
  input   [7:0]       arlen_sram_slv_axi4_s;        //read length of sram_slv_axi4_s AXI bus AR Channel
  input   [2:0]       arsize_sram_slv_axi4_s;       //read size of sram_slv_axi4_s AXI bus AR Channel
  input   [1:0]       arburst_sram_slv_axi4_s;      //read burst length of sram_slv_axi4_s AXI bus AR Channel
  input               arlock_sram_slv_axi4_s;       //read lock of sram_slv_axi4_s AXI bus AR Channel
  input   [3:0]       arcache_sram_slv_axi4_s;      //read cache field of sram_slv_axi4_s AXI bus AR Channel
  input   [2:0]       arprot_sram_slv_axi4_s;       //read prot field of sram_slv_axi4_s AXI bus AR Channel
  input               arvalid_sram_slv_axi4_s;      //read valid of sram_slv_axi4_s AXI bus AR Channel
  output              arready_sram_slv_axi4_s;      //read ready of sram_slv_axi4_s AXI bus AR Channel

  //R Channel
  output  [3:0]       rid_sram_slv_axi4_s;          //read id of sram_slv_axi4_s AXI bus R Channel
  output  [63:0]      rdata_sram_slv_axi4_s;        //read data of sram_slv_axi4_s AXI bus R Channel
  output  [1:0]       rresp_sram_slv_axi4_s;        //read response status of sram_slv_axi4_s AXI bus R Channel
  output              rlast_sram_slv_axi4_s;        //read last of sram_slv_axi4_s AXI bus R Channel
  output              rvalid_sram_slv_axi4_s;       //read valid of sram_slv_axi4_s AXI bus R Channel
  input               rready_sram_slv_axi4_s;       //read ready of sram_slv_axi4_s AXI bus R Channel

  //Clock and reset signals
  input               aclk;                         //main clock
  input               aresetn;                      //main reset



  //----------------------------------------------------------------------------
  // Internal wires
  //----------------------------------------------------------------------------



  wire           r_master_port_dst_valid;
  wire           r_master_port_dst_ready;
  wire           r_master_port_src_valid;
  wire           r_master_port_src_ready;

  wire [70:0]    r_master_port_src_data;     // concatenation of the inputs
  wire [70:0]    r_master_port_dst_data;     // concatenation of the registered inputs



  wire           w_master_port_dst_valid;
  wire           w_master_port_dst_ready;
  wire           w_master_port_src_valid;
  wire           w_master_port_src_ready;

  wire [72:0]    w_master_port_src_data;     // concatenation of the inputs
  wire [72:0]    w_master_port_dst_data;     // concatenation of the registered inputs



  wire           b_master_port_dst_valid;
  wire           b_master_port_dst_ready;
  wire           b_master_port_src_valid;
  wire           b_master_port_src_ready;

  wire [5:0]     b_master_port_src_data;     // concatenation of the inputs
  wire [5:0]     b_master_port_dst_data;     // concatenation of the registered inputs


  //----------------------------------------------------------------------------
  // Internal AXI wires
  //----------------------------------------------------------------------------



  // ---------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------

  // aw Channel
  assign awid_sram_slv_axi4_m     = awid_sram_slv_axi4_s;
  assign awaddr_sram_slv_axi4_m   = awaddr_sram_slv_axi4_s;
  assign awlen_sram_slv_axi4_m    = awlen_sram_slv_axi4_s;
  assign awsize_sram_slv_axi4_m   = awsize_sram_slv_axi4_s;
  assign awburst_sram_slv_axi4_m  = awburst_sram_slv_axi4_s;
  assign awlock_sram_slv_axi4_m   = awlock_sram_slv_axi4_s;
  assign awcache_sram_slv_axi4_m  = awcache_sram_slv_axi4_s;
  assign awprot_sram_slv_axi4_m   = awprot_sram_slv_axi4_s;
  assign awvalid_sram_slv_axi4_m  = awvalid_sram_slv_axi4_s;
  assign awready_sram_slv_axi4_s  = awready_sram_slv_axi4_m;
  // ar Channel
  assign arid_sram_slv_axi4_m     = arid_sram_slv_axi4_s;
  assign araddr_sram_slv_axi4_m   = araddr_sram_slv_axi4_s;
  assign arlen_sram_slv_axi4_m    = arlen_sram_slv_axi4_s;
  assign arsize_sram_slv_axi4_m   = arsize_sram_slv_axi4_s;
  assign arburst_sram_slv_axi4_m  = arburst_sram_slv_axi4_s;
  assign arlock_sram_slv_axi4_m   = arlock_sram_slv_axi4_s;
  assign arcache_sram_slv_axi4_m  = arcache_sram_slv_axi4_s;
  assign arprot_sram_slv_axi4_m   = arprot_sram_slv_axi4_s;
  assign arvalid_sram_slv_axi4_m  = arvalid_sram_slv_axi4_s;
  assign arready_sram_slv_axi4_s  = arready_sram_slv_axi4_m;

  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at Master Port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign w_master_port_src_data = {wdata_sram_slv_axi4_s,
        wstrb_sram_slv_axi4_s,
        wlast_sram_slv_axi4_s};

  // expand the concatenated registered values to the master port outputs
  assign {wdata_sram_slv_axi4_m,
        wstrb_sram_slv_axi4_m,
        wlast_sram_slv_axi4_m} = w_master_port_dst_data;

  assign wvalid_sram_slv_axi4_m = w_master_port_dst_valid;
  assign w_master_port_dst_ready = wready_sram_slv_axi4_m;

  assign w_master_port_src_valid = wvalid_sram_slv_axi4_s;
  assign wready_sram_slv_axi4_s = w_master_port_src_ready;


  // ---------------------------------------------------------------------------
  // R Channel timing block wiring at Master Port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign r_master_port_src_data = {rid_sram_slv_axi4_m,
        rdata_sram_slv_axi4_m,
        rresp_sram_slv_axi4_m,
        rlast_sram_slv_axi4_m};

  // expand the concatenated registered values to the master port outputs
  assign {rid_sram_slv_axi4_s,
        rdata_sram_slv_axi4_s,
        rresp_sram_slv_axi4_s,
        rlast_sram_slv_axi4_s} = r_master_port_dst_data;

  assign rvalid_sram_slv_axi4_s =  r_master_port_dst_valid;
  assign r_master_port_dst_ready = rready_sram_slv_axi4_s;

  assign r_master_port_src_valid = rvalid_sram_slv_axi4_m;
  assign rready_sram_slv_axi4_m = r_master_port_src_ready;


  // ---------------------------------------------------------------------------
  // B Channel timing block wiring at Master Port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign b_master_port_src_data = {bid_sram_slv_axi4_m,
        bresp_sram_slv_axi4_m};

  // expand the concatenated registered values to the master port outputs
  assign {bid_sram_slv_axi4_s,
        bresp_sram_slv_axi4_s} = b_master_port_dst_data;

  assign bvalid_sram_slv_axi4_s =  b_master_port_dst_valid;
  assign b_master_port_dst_ready = bready_sram_slv_axi4_s;

  assign b_master_port_src_valid = bvalid_sram_slv_axi4_m;
  assign bready_sram_slv_axi4_m = b_master_port_src_ready;




  // ---------------------------------------------------------------------------
  // Instantiation of Timing Isolation Blocks
  // ---------------------------------------------------------------------------

  //  R Channel Timing Isolation Register Block on master_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 71
  nic400_amib_sram_slv_axi4_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       71  // Payload Width
     )
  u_r_master_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn),
     .aclk                  (aclk),
     // inputs
     .src_valid             (r_master_port_src_valid),
     .src_data              (r_master_port_src_data),
     .dst_ready             (r_master_port_dst_ready),

     // outputs
     .src_ready             (r_master_port_src_ready),
     .dst_data              (r_master_port_dst_data),
     .dst_valid             (r_master_port_dst_valid)
     );



  //  W Channel Timing Isolation Register Block on master_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 73
  nic400_amib_sram_slv_axi4_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       73  // Payload Width
     )
  u_w_master_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn),
     .aclk                  (aclk),
     // inputs
     .src_valid             (w_master_port_src_valid),
     .src_data              (w_master_port_src_data),
     .dst_ready             (w_master_port_dst_ready),

     // outputs
     .src_ready             (w_master_port_src_ready),
     .dst_data              (w_master_port_dst_data),
     .dst_valid             (w_master_port_dst_valid)
     );



  //  B Channel Timing Isolation Register Block on master_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 6
  nic400_amib_sram_slv_axi4_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       6  // Payload Width
     )
  u_b_master_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn),
     .aclk                  (aclk),
     // inputs
     .src_valid             (b_master_port_src_valid),
     .src_data              (b_master_port_src_data),
     .dst_ready             (b_master_port_dst_ready),

     // outputs
     .src_ready             (b_master_port_src_ready),
     .dst_data              (b_master_port_dst_data),
     .dst_valid             (b_master_port_dst_valid)
     );



  // AW channel is set to wires at master_port.

  // AR channel is set to wires at master_port.

  // AW channel is set to wires at slave_port.

  // AR channel is set to wires at slave_port.

  // R channel is set to wires at slave_port.

  // W channel is set to wires at slave_port.

  // B channel is set to wires at slave_port.


endmodule

`include "nic400_amib_sram_slv_axi4_undefs_ysyx_rv32.v"

// --================================= End ===================================--
